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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Rev. 07 -- 29 January 2010 Product data sheet
1. General description
The NXP Semiconductors SE97 measures temperature from -40 C to +125 C with JEDEC Grade B 1 C accuracy between +75 C and +95 C and also provide 256 bytes of EEPROM memory communicating via the I2C-bus/SMBus. It is typically mounted on a Dual In-line Memory Module (DIMM) measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature Sensor Component specification and also replacing the Serial Presence Detect (SPD) which is used to store memory module and vendor information. The SE97 thermal sensor operates over the VDD range of 3.0 V to 3.6 V and the EEPROM over the range of 3.0 V to 3.6 V write and 1.7 V to 3.6 V read. Placing the Temp Sensor (TS) on a DIMM allows accurate monitoring of the DIMM module temperature to better estimate the DRAM case temperature (Tcase) to prevent it from exceeding the maximum operating temperature of 85 C. The chip set throttles the memory traffic based on the actual temperatures instead of the calculated worst-case temperature or the ambient temperature using a temp sensor mounted on the motherboard. There is up to 30 % improvement in thin and light notebooks that are using one or two 1 GB SO-DIMM modules. The TS is required on DDR3 RDIMM and RDIMM ECC. Future uses of the TS will include more dynamic control over thermal throttling, the ability to use the Alarm Window to create multiple temperature zones for dynamic throttling and to save processor time by scaling the memory refresh rate. The TS consists of a Analog-to-Digital Converter (ADC) that monitors and updates its own temperature readings 10 times per second, converts the reading to a digital data, and latches them into the data temperature register. User-programmable registers, the specification of upper/lower alarm and critical temperature trip points, EVENT output control, and temperature shutdown, provide flexibility for DIMM temperature-sensing applications. When the temperature changes beyond the specified boundary limits, the SE97 outputs an EVENT signal using an open-drain output that can be pulled up between 0.9 V and 3.6 V. The user has the option of setting the EVENT output signal polarity as either an active LOW or active HIGH comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. The EVENT output can even be configured as a critical temperature output. The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes (address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write Protected (RWP) by software. This allows DRAM vendor and product information to be stored and write protected. The upper 128 bytes (address 80h to FFh) are not write protected and can be used for general purpose data storage.
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
The SE97 has a single die for both the temp sensor and EEPROM for higher reliability and supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID registers provide the ability to confirm the identity of the device. Three address pins allow up to eight devices to be controlled on a single bus.
2. Features
2.1 General features
JEDEC (JC-42.4) TSE 2002B3 DIMM 0.5 C (typ.) between 75 C and 95 C temperature sensor plus 256-byte serial EEPROM for Serial Presence Detect (SPD) Optimized for voltage range: 3.0 V to 3.6 V, but SPD can be read down to 1.7 V Shutdown current: 0.1 A (typ.) and 5.0 A (max.) 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz SMBus ALERT Response Address and TIMEOUT (programmable) ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Available packages: TSSOP8, HVSON8, HXSON8, HWSON8 (JEDEC PSON8 VCED-3)
2.2 Temperature sensor features
11-bit ADC Temperature-to-Digital converter with 0.125 C resolution Operating current: 250 A (typ.) and 400 A (max.) Programmable hysteresis threshold: off, 0 C, 1.5 C, 3 C, 6 C Over/under/critical temperature EVENT output B grade accuracy: 0.5 C/1 C (typ./max.) +75 C to +95 C 1.0 C/2 C (typ./max.) +40 C to +125 C 2.0 C/3 C (typ./max.) -40 C to +125 C
2.3 Serial EEPROM features
Operating current: Write 0.6 mA (typ.) for 3.5 ms (typ.) Read 100 A (typ.) Organized as 1 block of 256 bytes [(256 x 8) bits] 100,000 write/erase cycles and 10 years of data retention Permanent and Reversible Software Write Protect Software Write Protection for the lower 128 bytes
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
2 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
3. Applications
DDR2 and DDR3 memory modules Laptops, personal computers and servers Enterprise networking Hard disk drives and other PC peripherals
4. Ordering information
Table 1. Ordering information Topside Package mark Name SE97 SE97 97L S97 S97 TSSOP8 HVSON8 HXSON8 Description plastic thin shrink small outline package; 8 leads; body width 4.4 mm plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm Version SOT530-1 SOT908-1 SOT1052-1 SOT1069-1 SOT1069-2 Type number SE97PW SE97TK SE97TL[1] SE97TP[1][2][3] SE97TP/S900[1][2][3]
HWSON8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm HWSON8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm
[1] [2] [3]
SE97TL and SE97TP offer improved VPOR/EVENT IOL. Industry standard 2 mm x 3 mm x 0.8 mm package to JEDEC VCED-3 PSON8 in 8 mm x 4 mm pitch tape 4 k quantity reels. SOT1069-1 is manufactured in APHK Hong Kong and SOT1069-2 is manufactured in APB Bangkok. The third line of the topside marking will start with `P' for SPHK and `n' for APB.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
3 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
5. Block diagram
SE97
TEMPERATURE REGISTER CRITICAL ALARM TRIP UPPER ALARM TRIP LOWER ALARM TRIP CAPABILITY MANUFACTURING ID DEVICE/REV ID SMBus TIMEOUT/ALERT CONFIGURATION * * * * * * * HYSTERESIS SHUT DOWN TEMP SENSOR LOCK PROTECTION EVENT OUTPUT ON/OFF EVENT OUTPUT POLARITY EVENT OUTPUT STATUS CLEAR EVENT OUTPUT STATUS FFh NO WRITE PROTECT 80h 7Fh SOFTWARE WRITE PROTECT 00h
R 30 k to 800 k
POR BAND GAP TEMPERATURE SENSOR
VDD
VSS
11-BIT ADC EVENT
SMBus/I2C-BUS INTERFACE
FILTER
SCL SDA
2-kbit EEPROM 10 V OVERVOLTAGE
R 30 k to 800 k
A0
A1
R 30 k to 800 k
A2
POINTER REGISTER
002aab349
Fig 1.
Block diagram of SE97
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
4 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
6. Pinning information
6.1 Pinning
terminal 1 index area A0 A1 A0 A1 A2 VSS 1 2 3 4
002aab805
1 2
8 7
VDD EVENT SCL SDA
8
VDD EVENT SCL SDA
SE97TL
A2 VSS 3 4 6 5
SE97PW
7 6 5
002aad548
Transparent top view
Fig 2.
Pin configuration for TSSOP8
Fig 3.
Pin configuration for HXSON8
terminal 1 index area A0 A1 A2 VSS 1 2 8 7 VDD EVENT SCL A2 4 5 SDA VSS
002aab803
terminal 1 index area A0 A1 1 2 8 7 VDD EVENT SCL SDA
SE97TK
3 6
SE97TP
3 4 6 5
002aad768
Transparent top view
Transparent top view
Fig 4.
Pin configuration for HVSON8
Fig 5.
Pin configuration for HWSON8 (SOT1069-1)
terminal 1 index area A0 A1 A2 VSS 1 2 3 4
SE97TP/S900
8 7 6 5 VDD EVENT SCL SDA
002aaf007
Transparent top view
Fig 6.
Pin configuration for HWSON8 (SOT1069-2)
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
5 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
6.2 Pin description
Table 2. Symbol A0 A1 A2 VSS SDA SCL EVENT VDD Pin description Pin 1 2 3 4 5 6 7 8 Type I I I ground I/O I O power Description I2C-bus/SMBus slave address bit 0 with internal pull-down. This input is overvoltage tolerant to support software write protection. I2C-bus/SMBus slave address bit 1 with internal pull-down I2C-bus/SMBus slave address bit 2 with internal pull-down device ground SMBus/I2C-bus serial data input/output (open-drain). Must have external pull-up resistor. SMBus/I2C-bus serial clock input/output (open-drain). Must have external pull-up resistor. Thermal alarm output for high/low and critical temperature limit (open-drain). Must have external pull-up resistor. device power supply (3.0 V to 3.6 V); supports 1.7 V for EEPROM read only.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
6 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7. Functional description
7.1 Serial bus interface
The SE97 communicates with a host controller by means of the 2-wire serial bus (I2C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The device supports SMBus, I2C-bus Standard-mode and Fast-mode. The I2C-bus standard speed is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus fast speed from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates the SCL signal, and the SE97 uses the SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant Bit (MSB) is transferred first. Since SCL and SDA are open-drain, pull-up resistors must be installed on these pins.
7.2 Slave address
The SE97 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address that allows a total of eight devices to coexist on the same bus. The A0, A1 and A2 pins are pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V software write protect. When it is driven higher than 7.8 V, writing a special command would put the EEPROM in reversible write protect mode (see Section 7.10.2 "Memory protection"). Each pin is sampled at the start of each I2C-bus/SMBus access. The temperature sensor's fixed address is `0011b'. The EEPROM's fixed address for the normal EEPROM read/write is `1010b', and for EEPROM software protection command is `0110b'. Refer to Figure 7.
slave address MSB 0 0 1 1 A2 A1 LSB A0
R/W MSB X 1 0
slave address LSB 1 0 A2 A1 A0
R/W MSB X 0 1
slave address LSB 1 0 A2 A1 A0
R/W
X
fixed
hardware selectable
002aab304
fixed
hardware selectable
002aab351
fixed
hardware selectable
002aab352
a. Temperature sensor Fig 7. Slave address
b. EEPROM (normal read/write)
c. EEPROM (software protection command)
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
7 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.3 EVENT output condition
The EVENT output indicates conditions such as the temperature crossing a predefined boundary. The EVENT modes are very configurable and selected using the configuration register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0], using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT (CONFIG[7]) bands can be locked. Figure 8 shows an example of the measured temperature versus time, with the corresponding behavior of the EVENT output in each of these modes. Upon device power-up, the default condition for the EVENT output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). EVENT output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT status can be read (CONFIG[4]) and cleared (CONFIG[5]).
* Advisory note:
- NXP device: After power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or bit 0 has no effect on the device operation. - Competitor device: Does not require that bit 3 be cleared (e.g., set back to (0)) before changing bit 2 or bit 0. - Work-around: In order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next byte. - SE97B will allow bit 2 or bit 0 to be changed even if bit 3 is set. If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT output, the output remains asserted during shutdown.
7.3.1 EVENT pin output voltage levels and resistor sizing
The EVENT open-drain output is typically pulled up to a voltage level from 0.9 V to 3.6 V with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the EVENT pin since it is simply an open-drain output. It could be pulled up to 0.1 V and would not affect the output. From the system perspective, there will be a practical limit. That limit will be the voltage necessary for the device monitoring the interrupt pin to detect a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another thing to consider is the value of the pull-up resistor. When a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the EVENT pin.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
8 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
temperature (C) critical Upper Boundary Alarm Tamb Ttrip(u) - Thys
Tth(crit) - Thys Ttrip(u) - Thys
Ttrip(l) - Thys Lower Boundary Alarm Ttrip(l) - Thys time EVENT in Comparator mode
EVENT in Interrupt mode
software interrupt clear EVENT in `Critical Temp only' mode
(1)
(2)
(1) (3)
(4)
(3)(5)
*
(6) (4)
(2) 002aae324
Refer to Table 3 for figure note information.
Fig 8. Table 3. Figure note
EVENT output condition EVENT output condition EVENT output boundary conditions EVENT output Comparator mode Interrupt mode Critical Temp only mode Temperature Register Status bits Bit 15 Above Critical Trip 0 0 0 0 1 0 Bit 14 Above Alarm Window 0 0 1 0 1 1 Bit 13 Below Alarm Window 0 1 0 0 0 0
(1) (2) (3) (4) (5) (6)
Tamb Ttrip(l) Tamb < Ttrip(l) - Thys Tamb > Ttrip(u) Tamb Ttrip(u) - Thys Tamb Tth(crit) Tamb < Tth(crit) - Thys
H L L H L L
L L L L L H
H H H H L H
When Tamb Tth(crit) and Tamb < Tth(crit) - Thys the EVENT output is in Comparator mode and bit 0 of CONFIG (EVENT output mode) is ignored.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
9 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.3.2 EVENT thresholds
7.3.2.1 Alarm window The device provides a comparison window with an UPPER trip point and a LOWER trip point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the upper temperature trip point, while the Lower Boundary Alarm Trip register holds the lower temperature trip point as modified by hysteresis as programmed in the Configuration register. When enabled, the EVENT output triggers whenever entering or exiting (crossing above or below) the alarm window.
* Advisory note:
- NXP Device: The EVENT output can be cleared through the Clear EVENT bit (CEVNT) or SMBus ALERT. - Competitor Device: The EVENT output can be cleared only through the Clear EVENT bit (CEVNT). - Work-around: Only clear EVENT output using the Clear EVENT bit (CEVNT). - There will be no change to NXP devices. The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm Trip.
* Advisory note:
- NXP device: Requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output. - Competitor devices: Compares the alarm limit with temperature register at any time, so they get the EVENT output immediately when new UPPER or LOWER Alarm Windows and the EVENT output are set at the same time. - Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1). - SE97B will compare alarm window and temperature register immediately. 7.3.2.2 Critical trip The Tth(crit) temperature setting is programmed in the Critical Alarm Trip register (04h) as modified by hysteresis as programmed in the Configuration register. When the temperature reaches the critical temperature value in this register (and EVENT is enabled), the EVENT output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. The Event cannot be cleared through the Clear EVENT bit (CEVNT) or SMBus ALERT. The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip.
* Advisory note:
- NXP device: Requires one conversion cycle (125 ms) after setting the Alarm Window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
10 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
- Competitor devices: Compares the Alarm Window with temperature register at any time, so they get the EVENT output immediately when new Tth(crit) and EVENT output are set at the same time. - Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1). Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before EVENT output is enabled and Event value is checked. 1. Set Tth(crit). 2. Doing something else (make sure that exceeds 125 ms). 3. Enable the EVENT output (EOCTL = 1). 4. Wait 20 s. 5. Read Event value. - SE97B will compare alarm window and temperature register immediately.
7.3.3 EVENT operation modes
7.3.3.1 Comparator mode In comparator mode, the EVENT output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the Upper Boundary Alarm Trip register or below the value programmed in the Lower Boundary Alarm Trip register or above the Critical Alarm Trip resister if Tth(crit) only is selected). Reads/writes on the registers do not affect the EVENT output in comparator mode. The EVENT signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. The comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 Interrupt mode In interrupt mode, EVENT asserts whenever the temperature crosses an alarm window threshold. After such an event occurs, writing a 1 to the Clear EVENT bit (CEVNT) in the configuration register de-asserts the EVENT output until the next trigger condition occurs. In interrupt mode, EVENT asserts when the temperature crosses the alarm upper boundary. If the EVENT output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, EVENT asserts again. Because the temperature is greater than the critical temperature threshold, a Clear EVENT command does not clear the EVENT output. Once the temperature drops below the critical temperature, EVENT de-asserts immediately.
* Advisory note:
- NXP device: If the EVENT output is not cleared before the temperature goes above the critical temperature threshold EVENT de-asserts immediately when temperature drops below the critical temperature. - Competitor devices: If the EVENT output is not cleared before or when the temperature is in the critical temperature threshold, EVENT will remain asserted after the temperature drops below the critical temperature until a Clear EVENT command.
SE97_7 (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
- Work-around: Always clear the EVENT output before temperature exceeds the critical temperature. - SE97B will keep EVENT asserted after the temperature drops below the critical temperature until a Clear EVENT command de-asserts EVENT.
7.4 Conversion rate
The conversion time is the amount of time required for the ADC to complete a temperature measurement for the local temperature sensor. The conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one second--the faster the conversion rate, the faster the temperature reading is updated. The SE97's conversion rate is at least 8 Hz or 125 ms.
7.4.1 What temperature is read when conversion is in progress
The SE97 has been designed to ensure a valid temperature is always available. When a read to the temperature register is initiated through the SMBus, the device checks to see if the temperature conversion process (Analog-to-Digital conversion) is complete and a new temperature is available:
* If the temperature conversion process is complete, then the new temperature value is
sent out on the SMBus.
* If the temperature conversion process in not complete, then the previous temperature
value is sent out on the SMBus. It is possible that while SMBus Master is reading the temperature register, a new temperature conversion completes. However, this will not affect the data (MSB or LSB) that is being shifted out. On the next read of the temperature register, the new temperature value will be shifted out.
7.5 Power-up default condition
After power-on, the SE97 is initialized to the following default condition:
* * * * *
Starts monitoring local sensor EVENT register is cleared; EVENT output is pulled HIGH by external pull-ups EVENT hysteresis is defaulted to 0 C Command pointer is defaulted to `00h' Critical Temp, Alarm Temperature Upper and Lower Boundary Trip register are defaulted to 0 C
* Capability register is defaulted to `0017h' for the B grade * Operational mode: comparator * SMBus register is defaulted to `00h' 7.6 Device initialization
SE97 temperature sensors have programmable registers, which, upon power-up, default to zero. The open-drain EVENT output is default to being disabled, comparator mode and active LOW. The alarm trigger registers default to being unprotected. The configuration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT
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Product data sheet
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
feature defaults to being enabled and can be programmed to disable. These registers are required to be initialized before the device can properly function. Except for the SPD, which does not have any programmable registers, and does not need to be initialized. Table 4 shows the default values and the example value to be programmed to these registers.
Table 4. Register 01h Registers to be initialized Default value 0000h Example value 0209h Description Configuration register
* * *
02h 03h 04h 22h 0000h 0000h 0000h 0000h 0550h 1F40h 05F0h 0000h
hysteresis = 1.5 C EVENT output = Interrupt mode EVENT output is enabled
Upper Boundary Alarm Trip register = 85 C Lower Boundary Alarm Trip register = -20 C Critical Alarm Trip register = 95 C SMBus register = no change
7.7 SMBus time-out
The SE97 supports SMBus time-out feature. If the host holds SCL LOW between 25 ms and 35 ms, the SE97 would reset its internal state machine to the bus IDLE state to prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out is disabled by writing a `1' to bit 7 of register 22h. Remark: When SMBus time-out is enabled, the I2C-bus minimum bus speed is limited by the SMBus time-out specification limit of 10 kHz. The SE97 has no SCL driver, so it cannot hold the SCL line LOW. Remark: SMBus time-out works over the entire supply range of 1.7 V to 3.6 V unless the shutdown bit (SHMD) is set and turns off the oscillator.
7.8 SMBus ALERT Response Address (ARA)
The SE97 supports SMBus ALERT when it is programmed for the Interrupt mode and when the EVENT polarity bit is set to `0'. The EVENT pin can be ANDed with other EVENT or interrupt signals from other slave devices to signal their intention to communicate with the host controller. When the host detects EVENT or other interrupt signal LOW, it issues an ARA to which a slave device would respond with its address. When there are multiple slave devices generating an ALERT the SE97 performs bus arbitration with the other slaves. If it wins the bus, it responds to the ARA and then clears the EVENT pin. Remark: Either in comparator mode or when the SE97 crosses the critical temperature, the host must also read the EVENT status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. Otherwise, the EVENT pin will not get de-asserted. Remark: In the SE97 the ARA is set to default ON. However, in the SE97B the ARA will be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
13 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
START bit
read Alert Response Address 0 0 1 1 0 0 1
acknowledge device address 0 0 0 1 1 A2
no acknowledge
STOP bit
S host detects SMBus ALERT
0
A1
A0
0
1
P
master sends a START bit, ARA and a read command
Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'.
host NACK and sends a STOP bit
002aac685
Fig 9.
How SE97 responds to SMBus ALERT Response Address
7.9 SMBus/I2C-bus interface
The data registers in this device are selected by the Pointer register. At power-up, the Pointer register is set to `00h', the location for the Capability register. The Pointer register latches the last location to which it was set. Each data register falls into one of three types of user accessibility:
* Read only * Write only * Write/Read same address
A `write' to this device will always include the address byte and the pointer byte. A write to any register other than the Pointer register requires two data bytes. Reading this device can take place either of two ways:
* If the location latched in the Pointer register is correct (most of the time it is expected
that the Pointer register will point to one of the Temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes.
* If the Pointer register needs to be set, then an address byte, pointer byte,
repeat START, and another address byte will accomplish a read. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). It takes this device 125 ms to measure the temperature. Refer to timing diagrams Figure 10 to Figure 13 for how to program the device.
1 SCL SDA S START A6
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A5
A4
A3
A2
A1
A0 W A ACK by device
D7
D6
D5
D4
D3
D2
D1
D0 A P ACK STOP by device
002aab308
device address and write
register address
A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 10. SMBus/I2C-bus write to the Pointer register
SE97_7
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Product data sheet
Rev. 07 -- 29 January 2010
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
1 SCL SDA S START by host 1 SCL SDA by host D15 A6
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 (cont.)
A5
A4
A3
A2
A1
A0 W A
D7 ACK by device 8 9 1
D6
D5
D4
D3
D2
D1
D0 A
(cont.)
device address and write 2 3 4 5 6 7
write register address 2 3 4 5 6 7
ACK by device 8 9
D14
D13
D12
D11
D10
D9
D8 A ACK by device
D7
D6
D5
D4
D3
D2
D1
D0 A P ACK STOP by device by host
002aab412
most significant byte data
least significant byte data
A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 11. SMBus/I2C-bus write to the Pointer register followed by a write data word
1 SCL SDA S START by host 1 SCL SDA SR repeated START by host SCL SDA D15 A6 A6
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 (cont.)
A5
A4
A3
A2
A1
A0 W A ACK by device
D7
D6
D5
D4
D3
D2
D1
D0 A
(cont.) ACK by device
device address and write 2 3 4 5 6 7 8
read register address
9 (cont.)
A5
A4
A3
A2
A1
A0 R A ACK by device
(cont.)
device address and read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D14
D13
D12
D11
D10
D9
D8 A ACK by host
D7
D6
D5
D4
D3
D2
D1
D0 A P NACK STOP by host by host
002aac686
returned most significant byte data
returned least significant byte data
A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 12. SMBus/I2C-bus write to Pointer register followed by a repeated START and an immediate data word read
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DDR memory module temp sensor with integrated SPD, 3.3 V
1 SCL SDA S START by host 1 SCL SDA D15 A6
2
3
4
5
6
7
8
9 (cont.)
A5
A4
A3
A2
A1
A0 R A ACK by device
(cont.)
device address and read 2 3 4 5 6 7 8
9
1
2
3
4
5
6
7
8
9
D14
D13
D12
D11
D10
D9
D8 A ACK by host
D7
D6
D5
D4
D3
D2
D1
D0 A P NACK STOP by host
002aac687
returned most significant byte data
returned least significant byte data
A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 13. SMBus/I2C-bus word read from register with a pre-set pointer
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.10 EEPROM operation
The 2-kbit EEPROM is organized as either 256 bytes of 8 bits each (byte mode), or 16 pages of 16 bytes each (page mode). Accessing the EEPROM in byte mode or page mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported. Communication with the EEPROM is via the 2-wire serial I2C-bus or SMBus. Figure 14 provides an overview of the EEPROM partitioning.
00h 01h FFh
...
07h
no write protect
80h 7Fh
16 pages or 256 bytes
write protect by software 0Fh 00h 1 page or 16 bytes
8 pages or 128 bytes
002aac812
Fig 14. EEPROM partitioning
The EEPROM can be read over voltage range 1.7 V to 3.6 V, but all write operations must be done 3.0 V to 3.6 V.
7.10.1 Write operations
7.10.1.1 Byte Write In Byte Write mode the master creates a START condition and then broadcasts the slave address, byte address, and data to be written. The slave acknowledges all 3 bytes by pulling down the SDA line during the ninth clock cycle following each byte. The master creates a STOP condition after the last ACK from the slave, which then starts the internal write operation (see Figure 15). During internal write, the slave will ignore any read/write request from the master.
slave address (memory) SDA S 1 0 1 0 A2 A1 A0 0 A
word address A
data DATA A P
START condition
R/W acknowledge from slave
acknowledge from slave
acknowledge from slave STOP condition; write to the memory is performed
002aab246
Fig 15. Byte Write timing
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DDR memory module temp sensor with integrated SPD, 3.3 V
7.10.1.2
Page Write The SE97 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page is selected by the four Most Significant Bits (MSB) of the address byte presented to the device after the slave address, while the four Least Significant Bits (LSB) point to the byte within the page. By loading more than one data byte into the device, up to an entire page can be written in one write cycle (see Figure 16). The internal byte address counter will increment automatically after each data byte. If the master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around fashion within the selected page. The internal write cycle is started following the STOP condition created by the master.
slave address (memory) SDA S 1 0 1 0 A2 A1 A0 0 A
word address A
data to memory DATA n A
START condition
R/W acknowledge from slave
acknowledge from slave
acknowledge from slave data to memory DATA n + 15 A P
acknowledge from slave STOP condition; write to the memory is performed
002aab247
Fig 16. Page Write timing
7.10.1.3
Acknowledge polling Acknowledge polling can be used to determine if the SE97 is busy writing or is ready to accept commands. Polling is implemented by sending a `Selective Read' command (described in Section 7.10.3 "Read operations") to the device. The SE97 will not acknowledge the slave address as long as internal write is in progress.
7.10.2 Memory protection
The lower half (the first 128 bytes) of the memory can be write protected by special EEPROM commands without an external control pin. The SE97 features three types of memory write protection instructions, and three respective read Protection instructions. The level of write-protection (set or clear) that has been defined using these instructions remained defined even after power cycle. The memory protection commands are:
* * * * * *
SE97_7
Permanent Write Protection (PWP) Reversible Write Protection (RWP) Clear Write Protection (CWP) Read Permanent Write Protection (RPWP) Read Reversible Write Protection (RRWP) Read Clear Write Protection (RCWP)
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DDR memory module temp sensor with integrated SPD, 3.3 V
Table 5 is the summary for normal and memory protection instructions.
Table 5. Command EEPROM commands summary Fixed address Bit 7[1] Normal EEPROM read/write Reversible Write Protection (RWP) Clear Reversible Write Protection (CRWP) Permanent Write Protection (PWP)[2] Read RWP Read CRWP Read PWP
[1] [2] [3] The most significant bit, bit 7, is sent first. A0, A1, and A2 are compared against the respective external pins on the SE97. VI(ov) ranges from 7.8 V to 10 V.
Hardware selectable address Bit 5 1 1 1 1 1 1 1 Bit 4 0 0 0 0 0 0 0 Bit 3 A2 VSS VSS A2 VSS VSS A2 Bit 2 A1 VSS VDD A1 VSS VDD A1 Bit 1 A0 VI(ov) VI(ov) A0 VI(ov)[3] VI(ov) A0
[3] [3] [3]
R/W Bit 0 R/W 0 0 0 1 1 1
Bit 6 0 1 1 1 1 1 1
1 0 0 0 0 0 0
This special EEPROM command consists of a unique 4-bit fixed address (0110b) and the voltage level applied on the 3-bit hardware address. Normally, to address the memory array, the 4-bit fixed address is `1010b'. To access the memory protection settings, the 4-bit fixed address is `0110b'. Figure 17 and Figure 18 show the write and read protection sequence, respectively. Up to eight memory devices can be connected on a single I2C-bus. Each one is given a 3-bit on the hardware selectable address (A2, A1, A0) inputs. The device only responds when the 4-bit fixed and hardware selectable bits are matched. The 8th bit is the read/write bit. This bit is set to 1 or 0 for read and write protection, respectively. The corresponding device acknowledges during the ninth bit time when there is a match on the 7-bit address. The device does not acknowledge when there is no match on the 7-bit address or when the device is already in permanent write protection mode and is programmed with any write protection instructions (i.e., PWP, RWP, CWP).
slave address (memory) SDA S 0 1 1 0 A2 A1 A0 0 A X
dummy byte address X X X X X X X A X X
dummy data X X X X X X A P
START condition
R/W acknowledge(1) from slave
acknowledge(1) from slave
acknowledge(1) from slave STOP condition
002aab356
X = Don't Care (1) Refer to Table 6 regarding the exact state of the acknowledge bit.
Fig 17. Software Write Protect (write)
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DDR memory module temp sensor with integrated SPD, 3.3 V
slave address (memory) SDA S 0 1 1 0 A2 A1 A0 1 A X
dummy byte address X X X X X X X A X X
dummy data X X X X X X A P
START condition
R/W acknowledge(1) from slave
no acknowledge(1) from slave
no acknowledge(1) from slave STOP condition
002aac644
X = Don't Care (1) Refer to Table 7 regarding the exact state of the acknowledge bit.
Fig 18. Software Write Protect (read)
7.10.2.1
Permanent Write Protection (PWP) If the software write-protection has been set with the PWP instruction, the first 128 bytes of the memory are permanently write-protected. This write-protection cannot be cleared by any instruction, or by power-cycling the device. Also, once the PWP instruction has been successfully executed, the device no longer acknowledges any instruction (with 4-bit fixed address of 0110b) to access the write-protection settings.
7.10.2.2
Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP) If the software write-protection has been set with the RWP instruction, it can be cleared again with a CRWP instruction. The two instructions, RWP and CRWP have the same format as a Byte Write instruction, but with a different setting for the hardware address pins (as shown in Table 5). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all `Don't Care' (Figure 17). Another difference is that the voltage, VI(ov), must be applied on the A0 pin, and specific logical levels must be applied on the other two (A1 and A2), as shown in Table 5.
Table 6. Acknowledge when writing data or defining write protection Instructions with R/W bit = 0. Status Permanently protected Protected with RWP Instruction PWP, RWP or CRWP page or byte write in lower 128 bytes RWP CRWP PWP page or byte write in lower 128 bytes Not protected PWP or RWP CRWP page or byte write ACK NACK ACK NACK ACK ACK ACK ACK ACK ACK Address not significant address not significant not significant not significant address not significant not significant address ACK NACK ACK NACK ACK ACK ACK ACK ACK ACK Data byte not significant data not significant not significant not significant data not significant not significant data ACK NACK NACK NACK ACK ACK NACK ACK ACK ACK Write cycle (Tcy(W)) no no no yes yes no yes no yes
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DDR memory module temp sensor with integrated SPD, 3.3 V
7.10.2.3
Read Permanent Write Protection (RPWP), Read Reversible Write Protection (RRWP), and Read Clear Reversible Write Protection (RCRWP) Read PWP, RWP, and CRWP allow the SE97 to be read in write protection mode. The instruction format is the same as that of the write protection except that the 8th bit, R/W, is set to 1. Figure 18 shows the instruction format, while Table 7 shows the responses when the instructions are issued.
Table 7. Acknowledge when reading the write protection Instructions with R/W bit = 1. Status Permanently protected Protected with RWP Instruction RPWP, RRWP or RCRWP RRWP RCRWP RPWP Not protected RPWP, RRWP or RCRWP ACK NACK NACK ACK ACK ACK Address not significant not significant not significant not significant not significant ACK NACK NACK NACK NACK NACK Data byte not significant not significant not significant not significant not significant ACK NACK NACK NACK NACK NACK
7.10.3 Read operations
7.10.3.1 Current address read In Standby mode, the SE97 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the `previous' byte was the last byte in memory, then the address counter will point to the first memory byte, and so on. If the SE97 decodes a slave address with a `1' in the R/W bit position (Figure 19), it will issue an Acknowledge in the ninth clock cycle and will then transmit the data byte being pointed at by the address counter. The master can then stop further transmission by issuing a No Acknowledge on the ninth bit then followed by a STOP condition.
slave address (memory) SDA S 1 0 1 0 A2 A1 A0 1 A
data from memory A P
START condition
R/W acknowledge from slave
no acknowledge from master STOP condition
002aab251
Fig 19. Current address read timing
7.10.3.2
Selective read The read operation can also be started at an address different from the one stored in the address counter. The address counter can be `initialized' by performing a `dummy' write operation (Figure 20). The START condition is followed by the slave address (with the R/W bit set to `0') and the desired byte address. Instead of following-up with data, the master then issues a second START, followed by the `Current Address Read' sequence, as described in Section 7.10.3.1.
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
slave address (memory) SDA S 1 0 1 0 A2 A1 A0 0 A
word address A
START condition
R/W acknowledge from slave
acknowledge from slave
slave address (memory) S 1 0 1 0 A2 A1 A0 1 A
data from memory A P
START condition
R/W acknowledge from slave
no acknowledge from master STOP condition
002aac901
Fig 20. Selective read timing
7.10.3.3
Sequential read If the master acknowledges the first data byte transmitted by the SE97, then the device will continue transmitting as long as each data byte is acknowledged by the master (Figure 21). If the end of memory is reached during sequential Read, the address counter will `wrap around' to the beginning of memory, and so on. Sequential Read works with either `Immediate Address Read' or `Selective Read', the only difference being the starting byte address.
slave address (memory) SDA S 1 0 1 0 A2 A1 A0 1 A
data from memory DATA n A
data from memory DATA n + 1 A
START condition
R/W acknowledge from slave
acknowledge from master
acknowledge from master data from memory DATA n + X A P
no acknowledge from master STOP condition
002aab253
Fig 21. Sequential read timing
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.11 Hot plugging
The SE97 can be used in hot plugging applications. Internal circuitry prevents damaging current backflow through the device when it is powered down, but with the I2C-bus, EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. The 50 ns noise filter will filter out any insertion glitches from the state machine, which is very robust and not prone to false operation. The device needs a proper power-up sequence to reset itself, not only for the device I2C-bus and I/O initial states, but also to load specific pre-defined data or calibration data into its operational registers. The power-up sequence should occur correctly with a fast ramp rate and the I2C-bus active. The SE97 might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. If the SCL line is held LOW, the part will not exit the power-on reset mode since the part is held in reset until SCL is released.
8. Register descriptions
8.1 Register overview
This section describes all the registers used in the SE97. The registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold and the ADC, as well as reporting status. The device uses the pointer register to access these registers. Read registers, as the name implies, are used for read only, and the write registers are for write only. Any attempt to read from a write-only register will result in reading `0's. Writing to a read-only register will have no effect on the read even though the write command is acknowledged. The Pointer register is an 8-bit register. All other registers are 16-bit.
Table 8. n/a 00h 01h 02h 03h 04h 05h 06h 07h 08h to 21h 22h 23h to FFh Register summary Default state (hex) n/a 0017h 0000h 0000h 0000h 0000h n/a 1131h A200h A201h 0000h 0000h 0000h Register name Pointer register Capability register (B grade = 0017h) Configuration register Upper Boundary Alarm Trip register Lower Boundary Alarm Trip register Critical Alarm Trip register Temperature register Manufacturer ID register Device ID/Revision register for SE97PW, SE97TK Device ID/Revision register for SE97TP, SE97TL reserved registers SMBus register reserved registers
Address (hex)
A write to reserved registers my cause unexpected results which may result in requiring a reset by removing and re-applying its power.
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DDR memory module temp sensor with integrated SPD, 3.3 V
8.2 Capability register (00h, 16-bit read-only)
Table 9. Bit Symbol Default Access Bit Symbol Default Access
[1]
Capability register (address 00h) bit allocation 15 0 R 7 RFU 0 R 0 R 14 0 R 6 13 0 R 5 VHV 0[1] R 1 R 12 RFU 0 R 4 TRES 0 R 0 R 3 0 R 2 WRNG 1 R 0 R 1 HACC 1 R 0 R 0 BCAP 1 R 11 10 9 8
The SE97 A0 pin can support up to 10 V, but the final die was already taped out before the JC42.4 ballot 1435.00 register change could be implemented. Bit 5 is changed from `0' to `1' on the future 1.7 V to 3.6 V SE97B.
Table 10. Bit 15:6 5
Capability register (address 00h) bit description Symbol RFU VHV Description Reserved for future use; must be zero. High voltage standoff for pin A0. 0 -- default 1 -- This part can support a voltage up to 10 V on the A0 pin to support JC42.4 ballot 1435.00.
4:3 2 1 0
TRES WRNG HACC BCAP
Temperature resolution. 10 -- 0.125 C LSB (11-bit) Wider range. 1 -- can read temperatures below 0 C and set sign bit accordingly Higher accuracy (set during manufacture). 1 -- B grade accuracy Basic capability. 1 -- has Alarm and Critical Trips interrupt capability
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DDR memory module temp sensor with integrated SPD, 3.3 V
8.3 Configuration register (01h, 16-bit read/write)
Table 11. Bit Symbol Default Access Bit Symbol Default Access 0 R 7 CTLB 0 R/W 0 R 6 AWLB 0 R/W Table 12. Bit 10:9 Configuration register (address 01h) bit allocation 15 14 13 RFU 0 R 5 CEVNT 0 R/W 0 R 4 ESTAT 0 R/W 0 R 3 EOCTL 0 R/W 0 R/W 2 CVO 0 R/W 12 11 10 HEN 0 R/W 1 EP 0 R/W 9 8 SHMD 0 R/W 0 EMD 0 R/W
Configuration register (address 01h) bit description Description reserved for future use; must be `0'. Hysteresis Enable. 00 -- disable hysteresis (default) 01 -- enable hysteresis at 1.5 C 10 -- enable hysteresis at 3 C 11 -- enable hysteresis at 6 C When enabled, hysteresis is applied to temperature movement around trigger points. For example, consider the behavior of the `Above Alarm Window' bit (bit 14 of the Temperature register) when the hysteresis is set to 3 C. As the temperature rises, bit 14 will be set to `1' (temperature is above the alarm window) when the Temperature register contains a value that is greater than the value in the Alarm Temperature Upper Boundary register. If the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the Alarm Temperature Upper Boundary register minus 3 C. (Refer to Figure 8 and Table 13). Similarly, the `Below Alarm Window' bit (bit 13 of the Temperature register) will be set to `0' (temperature is equal to or above the Alarm Window Lower Boundary Trip register) when the value in the Temperature register is equal to or greater than the value in the Alarm Temperature Lower Boundary register. As the temperature decreases, bit 13 will be set to `1' when the value in the Temperature register is equal to or less than the value in the Alarm Temperature Lower Boundary register minus 3 C. Note that hysteresis is also applied to EVENT pin functionality. When either of the Critical Trip or Alarm Window lock bits is set, these bits cannot be altered until unlocked.
Symbol HEN
15:11 RFU
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DDR memory module temp sensor with integrated SPD, 3.3 V
Configuration register (address 01h) bit description ...continued Description Shutdown Mode. 0 -- enabled Temperature Sensor (default) 1 -- disabled Temperature Sensor When shut down, the thermal sensor diode and ADC are disabled to save power, no events will be generated. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be set until unlocked. However, it can be cleared at any time. Remark: SMBus Time-out works over the entire supply range of 1.7 V to 3.6 V unless the shutdown bit (SHMD) is set and turns off the oscillator.
Table 12. Bit 8
Symbol SHMD
*
The EEPROM read works over the entire supply range of 1.7 V to 3.6 V whether or not SHMD is set because it does not need oscillator to function. There is no undervoltage lockout, the device no longer responds at some voltage below 1.7 V. EEPROM write works over the supply range of 3.0 V to 3.6 V, but not if SHMD is set since the oscillator is needed to write to EEPROM. There is an undervoltage lockout around 2.7 V that disables the RRPROM write operation. Thermal sensor is operational over the supply range of 3.0 V to 3.6 V, but not if SHMD is set since the oscillator is needed. There is an undervoltage lockout around 2.7 V that disables the temp sensor.
*
*
Thermal sensor auto turn-off feature: It was determined during testing of the SE97TP on 5 May 2008 that the Thermal Sensor auto turn-off feature was not compatible with the JEDEC power supply maximum ramp rate of 70 ms to 100 ms (slowest ramp rate) and this feature was disabled for all SE97 samples/production devices tested after 6 May (wk 0818 date code is when the devices were assembled). If there is a slow ramp rate on the supply voltage to 3.3 V the SE97 would be EE read only and not Thermal Sensor. This is due to a feature integrated into the device to automatically turn off the oscillator and place the thermal sensor in shutdown if the SE97 was being used in SO-DIMM in notebook applications at 1.8 V to reduce the power consumption on the battery. The feature counts for 30 ms ( 5 ms) after the oscillator starts working (around 1.2 V to 1.7 V) and if at 30 ms the voltage is greater than 2.4 V, the oscillator is left on and the Thermal Sensor functions as normal. But if the voltage is less than 2.4 V at 30 ms, the oscillator is turned off and the SE97 will think the part is in SPD only mode defaulting to the oscillator and Thermal Sensor disabled (SHMD Shutdown Mode bit 8 = 1). The oscillator and Thermal Sensor can be re-enabled by writing a logic 0 to SHMD. It is important in RDIMM/server applications that the Thermal Sensor is working as the default condition since the Thermal Sensor needs to be compatible with the JEDEC power supply ramp rate (maximum ramp rate is 70 ms to 100 ms) so the Thermal Sensor auto turn-off feature was disabled starting on 6 May 2008 by changing a programmable bit on the device during final test. There is no change in performance of the SE97 with this feature turned off and was verified during characterization. There is no way to read the SE97 registers via the I2C-bus to determine if the Thermal Sensor auto turn-off feature is enabled or disabled. This is set in a factory only register. You need to check the date code or do an operational test (e.g., run up to < 2.4 V, hold, then go to 3.3 V, then read SHMD bit 8 in the Configuration register to see if it is set to logic 0 (e.g., oscillator running = feature disabled) or logic 1 (e.g., oscillator turned off = feature enabled)). The Thermal Sensor auto turn-off feature is active in all package options prior to wk 0818. The SE97TP and SE97TL were not yet released to production so there is a clear line at release/orderable devices versus samples with this feature disabled in all production devices.
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DDR memory module temp sensor with integrated SPD, 3.3 V
Configuration register (address 01h) bit description ...continued Description Critical Trip Lock bit. 0 -- Critical Alarm Trip register is not locked and can be altered (default) 1 -- Critical Alarm Trip register settings cannot be altered This bit is initially cleared. When set, this bit will return a `1', and remains locked until cleared by internal Power-on reset. This bit can be written with a single write and do not require double writes.
Table 12. Bit 7
Symbol CTLB
6
AWLB
Alarm Window Lock bit. 0 -- Upper and Lower Alarm Trip registers are not locked and can be altered (default) 1 -- Upper and Lower Alarm Trip registers setting cannot be altered This bit is initially cleared. When set, this bit will return a `1' and remains locked until cleared by internal power-on reset. This bit can be written with a single write and does not require double writes.
5
CEVNT
Clear EVENT (write only). 0 -- no effect (default) 1 -- clears active EVENT in Interrupt mode. Writing to this register has no effect in Comparator mode. When read, this register always returns zero.
4
ESTAT
EVENT Status (read only). 0 -- EVENT output condition is not being asserted by this device (default) 1 -- EVENT output pin is being asserted by this device due to Alarm Window or Critical Trip condition The actual event causing the EVENT can be determined from the Read Temperature register. Interrupt Events can be cleared by writing to the `Clear EVENT' bit (CEVNT). Writing to this bit will have no effect.
3
EOCTL
EVENT Output Control. 0 -- EVENT output disabled (default) 1 -- EVENT output enabled When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
2
CVO
Critical Event Only. 0 -- EVENT output on Alarm or Critical temperature event (default) 1 -- EVENT only if temperature is above the value in the critical temperature register When the Critical Trip or Alarm Window lock bit is set, this bit cannot be altered until unlocked.
*
Advisory note: - JEDEC specification requires only the Alarm Window lock bit to be set. - Work-around: Clear both Critical Trip and Alarm Window lock bits. - Future 1.7 V to 3.6 V SE97B will require only the Alarm Window lock bit to be set.
1
EP
EVENT Polarity. 0 -- active LOW (default) 1 -- active HIGH. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
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DDR memory module temp sensor with integrated SPD, 3.3 V
Configuration register (address 01h) bit description ...continued Description EVENT Mode. 0 -- comparator output mode (default) 1 -- interrupt mode When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
Table 12. Bit 0
Symbol EMD
Table 13. Action
Hysteresis enable Below Alarm Window bit (bit 13) Temperature slope Threshold temperature Ttrip(l) - Thys Ttrip(l) Above Alarm Window bit (bit 14) Temperature slope rising falling Threshold temperature Ttrip(u) Ttrip(u) - Thys Above Critical Trip bit (bit 15) Temperature slope rising falling Threshold temperature Tth(crit) Tth(crit) - Thys
sets clears
falling rising
current temperature temperature
critical alarm threshold hysteresis
upper alarm threshold hysteresis
lower alarm threshold hysteresis
time Above Critical Trip (register 05h; bit 15 = ACT bit) Above Alarm Window (register 05h; bit 14 = AAW bit) Below Alarm Window (register 05h; bit 13 = BAW bit) clear set clear
clear
set
clear
set
clear
002aac799
Fig 22. Hysteresis: how it works
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DDR memory module temp sensor with integrated SPD, 3.3 V
8.4 Temperature format
The temperature data from the temperature read back register is an 11-bit 2's complement word with the least significant bit (LSB) equal to 0.125 C (resolution).
* A value of 019Ch will represent 25.75 C * A value of 07C0h will represent 124 C * A value of 1E64h will represent -25.75 C.
The unused LSB (bit 0) is set to `0'. Bit 11 will have a resolution of 128 C. The upper 3 bits of the temperature register indicate Trip Status based on the current temperature, and are not affected by the status of the EVENT output. Table 14 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b.
Table 14. Degree Celsius and Temperature Data register Content of Temperature Data register Status bits = 000b Binary +125 C +25 C +1 C +0.25 C +0.125 C 0 C -0.125 C -0.25 C -1 C -20 C -25 C -55 C Hex 07D0h 0190h 0010h 0004h 0002h 0000h 1FFEh 1FFCh 1FF0h 1F40h 1E70h 1C90h Status bits = 111b Binary Hex E7D0h E190h E010h E004h E002h E000h FFFEh FFFCh FFF0h FF40h FE70h FC90h
Temperature
000 0 01111101 000 0 000 0 00011001 000 0 000 0 00000001 000 0 000 0 00000000 010 0 000 0 00000000 001 0 000 0 00000000 000 0 000 1 11111111 111 0 000 1 11111111 110 0 000 1 11111111 000 0 000 1 11110100 000 0 000 1 11100111 000 0 000 1 11001001 000 0
111 0 01111101 000 0 111 0 00011001 000 0 111 0 00000001 000 0 111 0 00000000 010 0 111 0 00000000 001 0 111 0 00000000 000 0 111 1 11111111 111 0 111 1 11111111 110 0 111 1 11111111 000 0 111 1 11110100 000 0 111 1 11100111 000 0 111 1 11001001 000 0
SE97_7
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.5 Temperature Trip Point registers
8.5.1 Upper Boundary Alarm Trip register (16-bit read/write)
The value is the upper threshold temperature value for Alarm mode. The data format is 2's complement with bit 2 = 0.25 C. `RFU' bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity.
Table 15. Bit Symbol Default Access Bit Symbol Default Access Table 16. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Upper Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 UBT 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 UBT 0 R/W 1 RFU 0 R 0 R/W 0 9 8
Upper Boundary Alarm Trip register bit description Symbol RFU SIGN UBT RFU Description reserved; always `0' Sign (MSB) Upper Boundary Alarm Trip Temperature (LSB = 0.25 C) reserved; always `0'
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.5.2 Lower Boundary Alarm Trip register (16-bit read/write)
The value is the lower threshold temperature value for Alarm mode. The data format is 2's complement with bit 2 = 0.25 C. RFU bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity.
Table 17. Bit Symbol Default Access Bit Symbol Default Access Table 18. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Lower Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 LBT 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 LBT 0 R/W 1 RFU 0 R 0 R/W 0 9 8
Lower Boundary Alarm Trip register bit description Symbol RFU SIGN LBT RFU Description reserved; always `0' Sign (MSB) Lower Boundary Alarm Trip Temperature (LSB = 0.25 C) reserved; always `0'
8.5.3 Critical Alarm Trip register (16-bit read/write)
The value is the critical temperature. The data format is 2's complement with bit 2 = 0.25 C. RFU bits will always report zero.
Table 19. Bit Symbol Default Access Bit Symbol Default Access Table 20. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Lower Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 CT 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 CT 0 R/W 1 RFU 0 R 0 R/W 0 9 8
Critical Alarm Trip register bit description Symbol RFU SIGN CT RFU Description reserved; always `0' Sign (MSB) Critical Alarm Trip Temperature (LSB = 0.25 C) reserved; always `0'
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.6 Temperature register (16-bit read-only)
Table 21. Bit Symbol Default Access Bit Symbol Default Access Table 22. Bit 15 0 R 0 R 0 R Temperature register bit allocation 15 ACT 0 R 7 14 AAW 0 R 6 13 BAW 0 R 5 12 SIGN 0 R 4 TEMP 0 R 0 R 0 R 0 R 0 R 3 0 R 2 11 10 TEMP 0 R 1 0 R 0 RFU 0 R 9 8
Temperature register bit description Description Above Critical Trip. Increasing Tamb: 0 -- Tamb < Tth(crit) 1 -- Tamb Tth(crit) Decreasing Tamb: 0 -- Tamb < Tth(crit) - Thys 1 -- Tamb Tth(crit) - Thys
Symbol ACT
14
AAW
Above Alarm Window. Increasing Tamb: 0 -- Tamb Ttrip(u) 1 -- Tamb > Ttrip(u) Decreasing Tamb: 0 -- Tamb Ttrip(u) - Thys 1 -- Tamb > Ttrip(u) - Thys
13
BAW
Below Alarm Window. Increasing Tamb: 0 -- Tamb Ttrip(l) 1 -- Tamb < Ttrip(l) Decreasing Tamb: 0 -- Tamb Ttrip(l) - Thys 1 -- Tamb < Ttrip(l) - Thys
12
SIGN
Sign bit. 0 -- positive temperature value 1 -- negative temperature value
11:1 0
TEMP RFU
Temperature Value (2's complement). (LSB = 0.125 C) reserved; always `0'
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DDR memory module temp sensor with integrated SPD, 3.3 V
8.7 Manufacturer's ID register (16-bit read-only)
The SE97 Manufacturer's ID register is intended to match NXP Semiconductors PCI SIG (1131h).
Table 23. Bit Symbol Default Access Bit Symbol Default Access 0 R 0 R 1 R 0 R 7 0 R 6 0 R 5 Manufacturer's ID register bit allocation 15 14 13 12 1 R 4 1 R 11 0 R 3 0 R 10 0 R 2 0 R 9 0 R 1 0 R 8 1 R 0 1 R Manufacturer ID
(continued)
8.8 Device ID register
The SE97 device ID is A2h. The device revision varies by device.
Table 24. Bit Symbol Default Access Bit Symbol Default Access
[1]
Device ID register bit allocation 15 1 R 7 0 R 14 0 R 6 0 R 13 1 R 5 0 R 12 0 R 4 0 R 11 0 R 3 0 R 10 0 R 2 0 R 9 1 R 1
[1]
8 0 R 0
[1]
Device ID
Device revision R R
00 for SE97PW, SE97TK (original) is 00h. 01 for SE97TL, SE97TP (improved VPOR and EVENT IOL) is 01h.
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.9 SMBus register
Table 25. Bit Symbol Default Access Bit Symbol Default Access Table 26. Bit 15:8 7 0 R 7 STMOUT 0 R/W 0 R 0 R 0 R 0 R 6 0 R 5 0 R 4 RFU 0 R 0 R 0 R SMBus Time-out register bit allocation 15 14 13 12 RFU 0 R 3 0 R 2 0 R 1 0 R 0 SALRT 0 R/W 11 10 9 8
SMBus Time-out register bit description Symbol RFU STMOUT Description reserved; always `0' SMBus time-out. 0 -- SMBus time-out is enabled (default) 1 -- disable SMBus time-out When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
6:1 0
RFU SALRT
reserved; always `0' SMBus ALERT Response Address (ARA). 0 -- SMBus ARA is enabled (default) 1 -- disable SMBus ARA When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
9. Application design-in information
In a typical application, the SE97 behaves as a slave device and interfaces to a bus master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host, and asserts when the temperature reading exceeds the programmed values in the alarm registers. The A0, A1 and A2 pins are directly connected to VDD or VSS without any pull-up resistors. The SDA and SCL serial interface pins are open-drain I/Os that require pull-up resistors, and are able to sink a maximum of 3 mA with a voltage drop less than 0.4 V. Typical pull-up values for SCL and SDA are 10 k, but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus.
3.3 V slave VDD
10 k (3x)
master
SCL
SE97
A0 A1 A2
SDA EVENT
HOST CONTROLLER
VSS
002aab354
Fig 23. Typical application showing SE97 interfacing with 3.3 V host
mother board 3.3 V
0.1 F 0.1 F 0.1 F 10 k 10 k 10 k 10 k
1.1 V VCC(B) VCC(A) B2 A2
VDD
SCL
SCL SDA EVENT HOST CONTROLLER
SE97
A0 A1 A2
SDA EVENT
PCA9509
B1 A1
VSS
EN
002aad262
Fig 24. SE97 interfacing with 1.1 V host controller
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
9.1 SE97 in memory module application
Figure 25 shows the SE97 being placed in the memory module application. The SE97 is centered in the memory module to monitor the temperature of the DRAM and also to provide a 2-kbit EEPROM as the Serial Presence Detect (SPD). In the event of overheating, the SE97 triggers the EVENT output and the memory controller throttles the memory bus to slow the DRAM. The memory controller can also read the SE97 and watch the DRAM thermal behavior, taking preventive measures when necessary.
DIMM
DRAM
DRAM
SE97
DRAM
DRAM
SMBus
EVENT
MEMORY CONTROLLER
CPU
002aac800
Fig 25. System application
9.2 Layout consideration
The SE97 does not require any additional components other than the host controller to read its temperature. It is recommended that a 0.1 F bypass capacitor between the VDD and VSS pins is located as close as possible to the power and ground pins for noise protection.
9.3 Thermal considerations
In general, self-heating is the result of power consumption and not a concern, especially with the SE97, which consumes very low power. In the event the SDA and EVENT pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 C. Equation 1 is the formula to calculate the effect of self-heating: T = R th ( j-a ) x [ ( V DD x I DD ( AV ) ) + ( V OL ( SDA ) x I OL ( sin k ) ( SDA ) ) + ( V OL ( EVENT ) x I OL ( sin k )EVENT ) ] where: T = Tj - Tamb Tj = junction temperature Tamb = ambient temperature Rth(j-a) = package thermal resistance VDD = supply voltage IDD(AV) = average supply current
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
VOL(SDA) = LOW-level output voltage on pin SDA VOL(EVENT) = LOW-level output voltage on pin EVENT IOL(sink)(SDA) = SDA output current LOW IOL(sink)EVENT = EVENT output current LOW Calculation example: Tamb (typical temperature inside the notebook) = 50 C IDD(AV) = 400 A VDD = 3.6 V Maximum VOL(SDA) = 0.4 V IOL(sink)(SDA) = 1 mA VOL(EVENT) = 0.4 V IOL(sink)EVENT = 3 mA Rth(j-a) of HVSON8 = 56 C/W Rth(j-a) of TSSOP8 = 160 C/W Self heating due to power dissipation for HVSON8 is: T = 56 x [ ( 3.6 x 0.4 ) + ( 0.4 x 3 ) + ( 0.4 x 1 ) ] = 56 C W x 3.04 mW = 0.17 C Self heating due to power dissipation for TSSOP8 is: T = 160 x [ ( 3.6 x 0.4 ) + ( 0.4 x 3 ) + ( 0.4 x 1 ) ] = 160 C W x 3.04 mV = 0.49 C (3) (2)
10. Limiting values
Table 27. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Vn VA0 Isink Tj(max) Tstg Parameter supply voltage voltage on any other pin voltage on pin A0 sink current maximum junction temperature storage temperature SDA, SCL, EVENT pins overvoltage input; A0 pin at SDA, SCL, EVENT pins Conditions Min -0.3 -0.3 -0.3 -1 -65 Max +4.2 +4.2 +12.5 +50.0 150 +165 Unit V V V mA C C
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
11. Characteristics
Table 28. SE97 thermal sensor characteristics VDD = 3.0 V to 3.6 V; Tamb = -40 C to +125 C; unless otherwise specified. Symbol Tlim(acc) Parameter temperature limit accuracy Conditions B grade; VDD = 3.3 V 10 % Tamb = 75 C to 95 C Tamb = 40 C to 125 C Tamb = -40 C to +125 C Tres Tconv Ef(conv) temperature resolution conversion period conversion rate error conversion time from STOP bit to conversion complete percentage error in programmed data -1.0 -2.0 -3.0 -30 < 0.5 < 1.0 < 2 0.125 100 +1.0 +2.0 +3.0 120 +30 C C C C ms % Min Typ Max Unit
SE97_7
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 29. DC characteristics VDD = 1.7 V to 3.6 V; Tamb = -40 C to +125 C; unless otherwise specified. These specifications are guaranteed by design. Symbol IDD(AV) Isd(VDD) VIH VIL VOL1 VOL2 VI(ov) VPOR Parameter average supply current supply voltage shutdown mode current HIGH-level input voltage LOW-level input voltage LOW-level output voltage 1 LOW-level output voltage 2 overvoltage input voltage power-on reset voltage Conditions SMBus inactive SMBus inactive SCL, SDA; VDD = 3.0 V to 3.6 V SCL, SDA; VDD = 3.0 V to 3.6 V VDD = 3.0 V; IOL = 3 mA VDD = 1.7 V; IOL = 1.5 mA pin A0; VI(ov) - VDD > 4.8 V power supply rising power supply falling SE97PW, SE97TK SE97TL, SE97TP IOL(sink)EVENT LOW-level output sink current on pin EVENT VOL1 = 0.4 V SE97PW, SE97TK SE97TL, SE97TP IOL(sink)(SDA) ILOH ILIH ILIL Ci(SCL/SDA) IL Ipd ZIL ZIH
[1]
[1]
Min 0.7 x VDD 7.8 0.1 0.6 2 6 3 -1.0 -1.0 -1.0 -1.0 30 800
Typ 250 0.1 5 1 -
Max 400 5.0 VDD + 1 0.3 x VDD 0.4 0.5 10 1.7 +1.0 +1.0 +1.0 +1.0 10 4.0 -
Unit A A V V V V V V V V mA mA mA A A A A pF A A k k
LOW-level output sink current on pin SDA HIGH-level output leakage current HIGH-level input leakage current LOW-level input leakage current SCL and SDA input capacitance leakage current pull-down current LOW-level input impedance HIGH-level input impedance
VOL2 = 0.5 V EVENT; VOH = VDD SDA, SCL; VI = VDD SDA, SCL; VI = VSS A0, A1, A2; VI = VSS on A0, A1, A2 internal; A0, A1, A2 pins; VI = 0.3VDD to VDD pins A0, A1, A2; VI < 0.3VDD pins A0, A1, A2
High-voltage input voltage applied to pin A0 during RWP and CRWP operations. The JEDEC specification is 7 V (min.) and 10 V (max.), but since the SE97 EEPROM write works only down to 3.0 V, the condition of VI(ov) > 4.8 V + VDD or > 4.8 V + 3.0 V was applied and the minimum voltage changed to 7.8 V. If VDD is 3.6 V then the minimum voltage is 8.4 V.
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Product data sheet
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
500 IDD(AV) (A) 400 VDD = 3.6 V 3.0 V
002aac910
5 Isd(VDD) (A) 3
002aac911
300
200
VDD = 3.6 V 1
100 -1 -40
3.0 V
0 -40
0
40
80
120 Tamb (C)
0
40
80
120 Tamb (C)
I2C-bus and EEPROM inactive.
I2C-bus, temp sensor and EEPROM inactive.
Fig 26. Average supply current
600 IDD(AV) (A) 500 VDD = 3.6 V 400 3.0 V 300
002aac912
Fig 27. Shutdown supply current
3.5 Tlim(acc) (C) 2.0 1.0 0 -1.0 -2.0 -3.5 -50
002aad769
200 -40
0
40
80
120 Tamb (C)
-25
0
25
50
75
125 100 Tamb (C)
Temp sensor and EEPROM active.
VDD = 3.0 V to 3.6 V.
Fig 28. Average supply current during EEPROM write
8.0 IOL (mA) 6.0 VDD = 3.0 V to 3.6 V 4.0 VDD = 1.7 V 2.0
002aad258
Fig 29. Typical temperature accuracy
30 IOL(sink)EVENT (mA) 20
002aad767
10 VDD = 3.7 V 3.3 V 2.9 V 1.7 V 75 125 100 Tamb (C) 0 -50 -25 0 25 50 75 125 100 Tamb (C)
0 -50
-25
0
25
50
VOL1 = 0.4 V.
VOL1 = 0.4 V.
Fig 30. EVENT output current SE97PW, SE97TK
Fig 31. EVENT output current SE97TL, SE97TP
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
25 IOL(sink)(SDA) (mA) 20 VDD = 3.6 V 15 3.0 V 10
002aac907
15 conversion rate (conv/s) 13
002aac908
11
9
5
7
0 -40
0
40
80
120 Tamb (C)
5 -40
0
40
80
120 Tamb (C)
VOL2 = 0.6 V.
VDD = 3.0 V to 3.6 V.
Fig 32. SDA output current
140 Tconv (ms) 120
002aac909
Fig 33. Conversion rate
5 Tcy(W) (ms) 4
002aac902
100 3 80
60 -40
0
40
80
120 Tamb (C)
2 -40
0
40
80
120 Tamb (C)
VDD = 3.0 V to 3.6 V.
VDD = 3.0 V to 3.6 V.
Fig 34. Conversion period
3.0 Vth (V) 2.8
002aac903
Fig 35. EEPROM write cycle time
1.6 Vth (V) 1.4
002aac904
2.6
2.4 1.2 2.2
2.0 -40
0
40
80
120 Tamb (C)
1.0 -40
0
40
80
120 Tamb (C)
For temp sensor conversion. VDD = 3.0 V to 3.6 V.
For EEPROM read operation. VDD = 1.7 V to 3.6 V.
Fig 36. Average power-on threshold voltage
Fig 37. Average power-on threshold voltage
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Product data sheet
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
120 thermal response (%) 80
(1) (2)
002aac905
5 temp error (C) 3
002aac914
40
1
0 0 1 2 3 4 time (s) 5
-1 102
103
104
105
106
107 108 noise frequency (Hz)
VDD = 3.0 V to 3.6 V. From 25 C (air) to 120 C (oil bath). (1) TSSOP8 (2) HVSON8, HWSON8, HXSON8
VDD = 3.3 V + 150 mV (p-p); 0.1 F AC coupling capacitor; no decoupling capacitor; Tamb = 25 C.
Fig 38. Package thermal response
Fig 39. Temperature error versus power supply noise frequency
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Product data sheet
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 30. SMBus AC characteristics VDD = 1.7 V to 3.6 V; Tamb = -40 C to +125 C; unless otherwise specified. These specifications are guaranteed by design. The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC to 400 kHz. Symbol fSCL tHIGH tLOW tto(SMBus) tr tf tSU;DAT th(i)(D) tHD;DAT tSU;STA tHD;STA tSU;STO tBUF tSP Parameter SCL clock frequency HIGH period of the SCL clock 70 % to 70 % LOW period of the SCL clock 30 % to 30 % SMBus time-out time rise time of both SDA and SCL signals fall time of both SDA and SCL signals data set-up time data input hold time data hold time set-up time for a repeated START condition hold time (repeated) START condition set-up time for STOP condition bus free time between a STOP and START condition pulse width of spikes that must be suppressed by the input filter data valid time output fall time power-on reset pulse time read power-up time write power-up time write cycle time power supply falling
[8] [8] [2] [2][3] [4] [5]
Conditions
Standard mode Min 10[1] 4000 4700 25 250 0 200 4700 4000 4000 4700 Max 100 35 1000 300 3450 50
Fast mode Min 10[1] 600 1300 25 20 100 0 200 600 600 600 1300 Max 400 35 300 300 900 50
Unit kHz ns ns ms ns ns ns ns ns ns ns ns ns ns
LOW period to reset SMBus
30 % of SDA to 70 % of SCL
[6]
tVD;DAT tf(o) tPOR tpu(R) tpu(W) Tcy(W)
[1] [2] [3] [4] [5] [6] [7] [8]
from clock
200 0.5 -
1 1 10
200 0.5 -
250 1 1 10
ns ns s ms ms ms
EEPROM power-up timing[7]
Write cycle limits
[9]
Minimum clock frequency is 0 kHz if SMBus Time-out is disabled. Delay from SDA STOP to SDA START. A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Delay from SCL HIGH-to-LOW transition to SDA edges. Delay from SCL LOW-to-HIGH transition to restart SDA. Delay from SDA START to first SCL HIGH-to-LOW transition. These parameters tested initially and after a design or process change that affects the parameter. tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated.
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
[9]
The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal write cycle, SDA is released by the slave and the device does not acknowledge external commands.
tLOW tr SCL tBUF tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;DAT VIH VIL P S S P tSU;STO tf VIH VIL
SDA
SCL tSU;STO tSU;STA
VIH VIL
SDA tW STOP condition write cycle START condition
VIH VIL
002aae750
S = START condition P = STOP condition
Fig 40. AC waveforms
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1
E D
A X
c y HE Z vMA
8
5
A2 A1 pin 1 index Lp L detail X
(A3)
A
1
e bp
4
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.13 D(1) 3.1 2.9 E(2) 4.5 4.3 e 0.65 HE 6.5 6.3 L 0.94 Lp 0.7 0.5 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT530-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-24 03-02-18
Fig 41. Package outline SOT530-1 (TSSOP8)
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NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm
SOT908-1
0
1 scale
2 mm
X
D
B
A
E
A A1 c detail X
terminal 1 index area terminal 1 index area
1
e1 e b
4
v w
M M
CAB C
C y1 C y exposed tie bar (4x)
L
Eh
exposed tie bar (4x)
8
5
Dh
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT908-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 05-09-26 05-10-05 A(1) max. 1 A1 0.05 0.00 b 0.3 0.2 c 0.2 D(1) 3.1 2.9 Dh 2.25 1.95 E(1) 3.1 2.9 Eh 1.65 1.35 e 0.5 e1 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Fig 42. Package outline SOT908-1 (HVSON8)
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SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
HXSON8: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm
SOT1052-1
X
b D
v
M
AB A
B
E
A
A1
detail X terminal 1 index area 1/2 e terminal 1 index area L e
1 4
C y1 C y
(8x)
Eh
8
5
Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A(1) 0.5 A1 0.04 b 0.3 0.2 D 2.1 2.0 1.9 D1 1.6 1.4 E 3.1 3.0 2.9 E1 1.6 0.5 1.4 0.35 e 1 scale L 0.45 0.1 0.05 0.05 v y y1 2 mm
Note 1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229 OUTLINE VERSION SOT1052-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 08-01-11 08-03-11
Fig 43. Package outline SOT1052-1 (HXSON8)
SE97_7 (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
47 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm
SOT1069-1
X
b D
v B
AB A
E
A A1
A2
A3
terminal 1 index area 1/2 e terminal 1 index area L K e
1 4
detail X C y1 C y
(8x)
E2
8
5
D2 0 Dimensions Unit mm A(1) A1 A2 A3 0.2 b 0.30 0.25 0.20 D 2.1 2.0 1.9 D2 1.6 1.4 E 3.1 3.0 2.9 E2 1.6 0.5 1.4 0.2 0.35
sot1069-1_po
1 scale e K
2 mm
L 0.45
v 0.1
y
y1
max 0.80 0.05 0.65 nom 0.75 0.02 0.55 min 0.70 0 0.45
0.05 0.05
Note 1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229 Outline version SOT1069-1 References IEC JEDEC MO-229 JEITA European projection
Issue date 08-07-10 09-08-10
Fig 44. Package outline SOT1069-1 (HWSON8)
SE97_7 (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
48 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm
SOT1069-2
X
D
B
A
A2 E A A1
A3
terminal 1 index area e1 terminal 1 index area 1 L K e b 4 v w CAB C y1 C
detail X
C y
E2
8 D2
5
0 Dimensions Unit mm A(1) A1 A2 A3 0.2 b 0.30 0.25 0.18 D(1) 2.1 2.0 1.9 D2 1.6 1.5 1.4 E(1) 3.1 3.0 2.9 E2 1.6 1.5 1.4
1 scale e 0.5 e1 1.5
2 mm
K
L
v 0.1
w
y
y1
max 0.80 0.05 0.65 nom 0.75 0.02 0.55 min 0.70 0.00 0.45
0.40 0.45 0.35 0.40 0.30 0.35
0.05 0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1069-2 References IEC --JEDEC MO-229 JEITA --European projection
sot1069-2_po
Issue date 09-10-22 09-11-18
Fig 45. Package outline SOT1069-2 (HWSON8)
SE97_7 (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
49 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
SE97_7 (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
50 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 46) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 31 and 32
Table 31. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 32. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 46.
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
51 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 46. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 33. Acronym ADC ARA CDM CMOS CPU DDR DIMM DRAM ECC EEPROM ESD HBM I2C-bus LSB MM MSB PC PCB POR
SE97_7
Abbreviations Description Analog-to-Digital Converter Alert Response Address Charged-Device Model Complementary Metal-Oxide Semiconductor Central Processing Unit Double Data Rate Dual In-line Memory Module Dynamic Random Access Memory Error-Correcting Code Electrically Erasable Programmable Read-Only Memory ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Least Significant Bit Machine Model Most Significant Bit Personal Computer Printed-Circuit Board Power-On Reset
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
52 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Abbreviations ...continued Description Registered Dual In-line Memory Module System Management Bus Small Outline Dual In-line Memory Module Serial Presence Detect
Table 33. Acronym RDIMM SMBus SO-DIMM SPD
15. Revision history
Table 34. SE97_7 Modifications: Revision history Release date 20100129 Data sheet status Product data sheet Change notice Supersedes SE97_6 Document ID
*
Table 1 "Ordering information": - added Type number SE97TP/S900 - added Table note [3]
* * * *
Added (new) Figure 6 "Pin configuration for HWSON8 (SOT1069-2)" Section 7.7 "SMBus time-out", 1st paragraph, second sentence: changed from "between 25 ns and 35 ms" to "between 25 ms and 35 ms" Table 8 "Register summary", address 07h (Device ID/Revision register): - Default state is split: A200h for SE97PW, SE97TK; A201h for SE97TP, SE97TL Section 8.8 "Device ID register": - 1st paragraph, 1st sentence: changed from "The SE97 device ID is A1h." to "The SE97 device ID is A2h." - Table note [1] modified
*
SE97_6 SE97_5 SE97_4 SE97_3 SE97_2 SE97_1
Added (new) Figure 45 "Package outline SOT1069-2 (HWSON8)" Product data sheet Product data sheet Product data sheet Product data sheet Product data sheet Objective data sheet SE97_5 SE97_4 SE97_3 SE97_2 SE97_1 -
20090817 20090806 20090130 20080715 20071012 20070524
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
53 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
SE97_7
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 -- 29 January 2010
54 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
18. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 Temperature sensor features . . . . . . . . . . . . . . 2 Serial EEPROM features . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Serial bus interface . . . . . . . . . . . . . . . . . . . . . . 7 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 7 EVENT output condition . . . . . . . . . . . . . . . . . . 8 EVENT pin output voltage levels and resistor sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3.2 EVENT thresholds . . . . . . . . . . . . . . . . . . . . . 10 7.3.2.1 Alarm window . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.2.2 Critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.3 EVENT operation modes . . . . . . . . . . . . . . . . 11 7.3.3.1 Comparator mode. . . . . . . . . . . . . . . . . . . . . . 11 7.3.3.2 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 Conversion rate . . . . . . . . . . . . . . . . . . . . . . . 12 7.4.1 What temperature is read when conversion is in progress . . . . . . . . . . . . . . . . 12 7.5 Power-up default condition . . . . . . . . . . . . . . . 12 7.6 Device initialization . . . . . . . . . . . . . . . . . . . . . 12 7.7 SMBus time-out . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 SMBus ALERT Response Address (ARA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9 SMBus/I2C-bus interface . . . . . . . . . . . . . . . . 14 7.10 EEPROM operation . . . . . . . . . . . . . . . . . . . . 17 7.10.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . 17 7.10.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10.1.3 Acknowledge polling . . . . . . . . . . . . . . . . . . . . 18 7.10.2 Memory protection . . . . . . . . . . . . . . . . . . . . . 18 7.10.2.1 Permanent Write Protection (PWP) . . . . . . . . 20 7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP) . . 20 7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection (RRWP), and Read Clear Reversible Write Protection (RCRWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.10.3 Read operations . . . . . . . . . . . . . . . . . . . . . . . 21 7.10.3.1 Current address read . . . . . . . . . . . . . . . . . . . 21 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.10.3.2 Selective read . . . . . . . . . . . . . . . . . . . . . . . . 7.10.3.3 Sequential read . . . . . . . . . . . . . . . . . . . . . . . 7.11 Hot plugging. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register descriptions . . . . . . . . . . . . . . . . . . . 8.1 Register overview . . . . . . . . . . . . . . . . . . . . . 8.2 Capability register (00h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 8.3 Configuration register (01h, 16-bit read/write). . . . . . . . . . . . . . . . . . 8.4 Temperature format . . . . . . . . . . . . . . . . . . . . 8.5 Temperature Trip Point registers . . . . . . . . . . 8.5.1 Upper Boundary Alarm Trip register (16-bit read/write). . . . . . . . . . . . . . . . . . . . . . 8.5.2 Lower Boundary Alarm Trip register (16-bit read/write). . . . . . . . . . . . . . . . . . . . . . 8.5.3 Critical Alarm Trip register (16-bit read/write). . . . . . . . . . . . . . . . . . . . . . 8.6 Temperature register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 8.7 Manufacturer's ID register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 8.8 Device ID register . . . . . . . . . . . . . . . . . . . . . 8.9 SMBus register . . . . . . . . . . . . . . . . . . . . . . . 9 Application design-in information. . . . . . . . . 9.1 SE97 in memory module application . . . . . . . 9.2 Layout consideration . . . . . . . . . . . . . . . . . . . 9.3 Thermal considerations . . . . . . . . . . . . . . . . . 10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 22 23 23 23 24 25 29 30 30 31 31 32 33 33 34 35 36 36 36 37 38 45 50 50 50 50 51 52 53 54 54 54 54 54 54 55
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 January 2010 Document identifier: SE97_7

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